順序回路をVerilogで書くテスト

初めてスクラッチで書いてみたらよくわかった。
環境はbasys2 Spartan 3E クロック50MHz

`timescale 1ns / 1ps
module LEDconnection(
	input mclk,
	output reg [7:0] Led 
    );

    reg[25:0] cnt;
    wire en1hz = (cnt==26'd49_999_999);

    always@ (posedge mclk) begin
	if(en1hz)
		cnt <= 26'd0;
	else
		cnt <= cnt + 26'd1;
    end

    reg [7:0] ledcount;
    wire en8 = (ledcount==8'd7);

    always@ (posedge mclk) begin
	if(en1hz)
		if(en8)
			ledcount <= 8'b0;
		else
			ledcount <= ledcount + 8'b1;
    end

    always @* begin
	    case(ledcount)
		    8'd0: Led = 8'b00000001;
		    8'd1: Led = 8'b00000010;
		    8'd2: Led = 8'b00000100;
		    8'd3: Led = 8'b00001000;
		    8'd4: Led = 8'b00010000;
		    8'd5: Led = 8'b00100000;
		    8'd6: Led = 8'b01000000;
		    8'd7: Led = 8'b10000000;
		    default: Led = 8'd0;
	    endcase
    end
    
endmodule