<snippet> <content><![CDATA[ always @(posedge CLK) begin if(RST) ${1:LED} <= ${2:8}'h0; else if () ${1:LED} <= ${2:8}'h0; else ${1:LED} <= ${1:LED} + ${2:8}'h1; end end ]]></content> <!-- Optional: Set a tabTrigger to define how to trigger the snippet --> <tabTrigger>ff</tabTrigger> <!-- Optional: Set a scope to limit where the snippet will trigger --> <scope>source.verilog</scope> </snippet>