2014-08-26から1日間の記事一覧

VHDLのテスト

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity ledblink is port ( CLK: in std_logic; RST: in std_logic; LED1: buffer std_logic ); end ledblink; architecture Behavioral of ledblink is signal cnt: integer range 0…