VHDLのテスト

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity ledblink is
	port (
		CLK: in std_logic;
		RST: in std_logic;
		LED1: buffer std_logic
	     );
end ledblink;
architecture Behavioral of ledblink is
	signal cnt: integer range 0 to 31_999_999;
	signal en1hz: std_logic;
begin
	en1hz <= '1' when (cnt=31_999_999) else '0';

	process (CLK) begin
		if(CLK'event and CLK='1') then
			if (en1hz='1') then
				cnt <= 0;
			elsif (RST='1') then
				cnt <= 0;
			else
				cnt <= cnt + 1;
			end if;
		end if;
	end process;

	process (CLK) begin
		if(CLK'event and CLK='1') then
			if(en1hz='1') then
				LED1 <= not LED1; 
			end if;
		end if;
	end process;


end Behavioral;