`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 04:32:07 07/31/2014 // Design Name: // Module Name: OneSecCounter // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module OneSecCounter( input CLK,RST, output reg[7:0] nSEG, output [3:0] nAN ); assign nAN = 4'b0101; reg [25:0] cnt; wire en1hz = (cnt == 26'd499_999_999); always@(posedge CLK) begin if (RST) cnt <= 26'b0; else if (en1hz) cnt <= 26'b0; else cnt <= cnt + 26'b1; end reg [3:0] sec; always@(posedge CLK) begin if(RST) sec <= 4'h0; else if (en1hz) if(sec==4'h9) sec <= 4'h0; else sec <= sec + 4'h1; end always@* begin case(sec) 4'h0: nSEG = 8'b11000000; 4'h1: nSEG = 8'b11111001; 4'h2: nSEG = 8'b10100100; 4'h3: nSEG = 8'b10110000; 4'h4: nSEG = 8'b10011001; 4'h5: nSEG = 8'b10010010; 4'h6: nSEG = 8'b10000010; 4'h7: nSEG = 8'b11011000; 4'h8: nSEG = 8'b10000000; 4'h9: nSEG = 8'b10010000; default: nSEG = 8'bxxxxxxxx; endcase end endmodule
ucf
# clock pin for Nexys 2 Board NET "CLK" LOC = "B8"; # 7 segment display NET "nSEG<0>" LOC = "L14"; # Bank = 1, Signal name = CA NET "nSEG<1>" LOC = "H12"; # Bank = 1, Signal name = CB NET "nSEG<2>" LOC = "N14"; # Bank = 1, Signal name = CC NET "nSEG<3>" LOC = "N11"; # Bank = 2, Signal name = CD NET "nSEG<4>" LOC = "P12"; # Bank = 2, Signal name = CE NET "nSEG<5>" LOC = "L13"; # Bank = 1, Signal name = CF NET "nSEG<6>" LOC = "M12"; # Bank = 1, Signal name = CG NET "nSEG<7>" LOC = "N13"; # Bank = 1, Signal name = DP NET "nAN<0>" LOC = "K14"; # Bank = 1, Signal name = AN3 NET "nAN<1>" LOC = "M13"; # Bank = 1, Signal name = AN2 NET "nAN<2>" LOC = "J12"; # Bank = 1, Signal name = AN1 NET "nAN<3>" LOC = "F12"; # Bank = 1, Signal name = AN0 # Switches NET "RST" LOC = "G12";