Zyboで音を出す

440Hz（A４）の音を出してみる
ここを参考に
http://d.hatena.ne.jp/kazunori_279/20121204/1354631391

zyboのPLをPLのみで動かす（PSを使用しない）

クロックはCLK125(125MHz)のL16から入れる

リセットは適当にボタンから入れる
hoge.xdc

set_property IOSTANDARD LVCMOS33 [get_ports CLK]
set_property IOSTANDARD LVCMOS33 [get_ports GEN]
set_property IOSTANDARD LVCMOS33 [get_ports LED]
set_property IOSTANDARD LVCMOS33 [get_ports RST]
set_property PACKAGE_PIN L16 [get_ports CLK]
set_property PACKAGE_PIN M14 [get_ports LED]
set_property PACKAGE_PIN M15 [get_ports GEN]
set_property PACKAGE_PIN R18 [get_ports RST]

HDL

`timescale 1ns / 1ps
module synth(
input CLK,
input RST,
output GEN,
output LED
    );
    
reg[31:0] cnt;
reg[31:0] cnt2;
reg led;
reg gen;
parameter A4_COUNT =32'h22ADD;
parameter ONE_SEC_COUNT = 32'h7735940;
wire en440hz = (cnt==A4_COUNT);
wire en1hz = (cnt2==ONE_SEC_COUNT);

always @(posedge CLK) begin
    if(RST) 
        cnt <= 32'h0;
    else if(en440hz)
        cnt <= 32'h0;  
    else
        cnt <= cnt + 32'h1;
end

always @(posedge CLK) begin
    if(RST) 
        cnt2 <= 32'h0;
    else if(en1hz)
        cnt2 <= 32'h0;  
    else
        cnt2 <= cnt2 + 32'h1;
end

always @(posedge CLK) begin
    if(RST) 
        led <= 1'b0;
    else if(en1hz)
        led <= ~led;  
end

always @(posedge CLK) begin
    if(RST) 
        gen <= 1'b0;
    else if(en440hz)
        gen <= ~gen;  
end

assign GEN=gen;
assign LED=led;    
    
endmodule